SIGDA, Super Compendium, CODES 2001, Table of Contents

CODES'01 TABLE OF CONTENTS

Topics: [1] [2] [3] [4] [5] [6] [7] [8] [9]

"s" indicates short paper

The Usage of Stochastic Processes in Embedded System Specifications [p. 5]: Axel Jantsch, Ingo Sander, Wenbiao Wu
Modeling and Evaluation of Hardware/Software Designs [p. 11]: Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas
SystemC: A Homogenous Environment to Test Embedded Systems [p. 17]: Alessandro Fin, Franco Fummi, Maurizio Martignano, Mirko Signoretto
"s" Embedded UML: a merger of real-time UML and co-design [p. 23]: Grant Martin, Luciano Lavagno, Jean Louis-Guerin

Hardware/Software Partitioning of embedded system in OCAPI-xl [p. 30]: G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M.Engels, I. Bolsens
HW/SW Partitioning of an Embedded Instruction Memory Decompressor [p. 36]: Shlomo Weiss, Shay Beren
"s" MAGELLAN: Multiway Hardware-Software Partitioning and Scheduling for Latency Minimization of Hierarchical Control Dataflow Task Graphs [p. 42]: Karam S. Chatha, Ranga Vemuri
A Practical Toolbox for System Level Communication Synthesis [p. 48]: Denis Hommais, Frédéric Pétrot, Ivan Augé
"s" System Canvas: A New Design Environment for Embedded DSP and Telecommunication Systems [p. 54]: Praveen K. Murthy, Etan G. Cohen, Steve Rowland

Designing Domain-Specific Processors [p. 61]: Marnix Arnold, Henk Corporaal
RS-FDRA: A Register Sensitive Software Pipelining Algorithm for Embedded VLIW Processors [p. 67]: Cagdas Akturan, Margarida F. Jacome
A Novel Parallel Deadlock Detection Algorithm and Architecture [p. 73]: Pun Hang Shiu, Yudong Tan, Vincent John Mooney III
Towards Effective Embedded Processors in Codesigns: Customizable Partitioned Caches [p. 79]: Peter Petrov, Alex Orailoglu

Development Cost and Size Estimation Starting from High-Level Specifications [p. 86]: William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini
Exploring Design Space of Parallel Realizations:MPEG-2 Decoder Case Study [p. 92]: Basant K. Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan
"s" Source-Level Execution Time Estimation of C Programs [p. 98]: Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
"s" STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems [p. 104]: Felice Balarin
"s" Evaluating Register File Size in ASIP Design [p. 109]: Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan

Generating Mixed Hardware/Software Systems from SDL Specifications [p. 116]: Frank Slomka, Matthias Dörfel, Ralf Münzenberger
Area-Efficient Buffer Binding Based on a Novel Two-Port FIFO Structure [p. 122]: Kyoungseok Rha, Kiyoung Choi
Deriving Hard Real-Time Embedded Systems Implementations directly from SDL Specifications [p. 128]: J.M. Alvarez, M Diaz, L. Llopis, E. Pimentel, J.M. Troya
A Trace Transformation Technique for Communication Refinement [p. 134]: Paul Lieverse, Pieter van der Wolf, Ed Deprettere
"s" A Systematic Approach to Software Peripherals for Embedded Systems [p. 140]: Dimitrios Lioupis, Apostolos Papagiannis, Dionysia Psihogiou

A Constructive Algorithm for Memory-Aware Task Assignment and Scheduling [p. 147]: Radoslaw Wlodzimierz Szymanek, Krzysztof Kuchcinski
A Constraint-based Application Model and Scheduling Techniques for Power-aware Systems [p. 153]: Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi Kurdahi
"s" Optimal Acyclic Fine-Grain Scheduling with Cache Effects for Embedded and Real Time Systems [p. 159]: Sid-Ahmed-Ali Touati
"s" Scheduling-based Code Size Reduction in Processors with Indirect Addressing Mode [p. 165]: Sungtaek Lim, Jihong Kim, Kiyoung Choi
"s" Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform [p. 170]: Chun Wong, Paul Marchal, Peng Yang, Aggeliki Prayati, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man

Parameterized System Design Based on Genetic Algorithms [p. 177]: Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
"s" Minimizing System Modification in an Incremental Design Approach [p. 183]: Paul Pop, Petru Eles, Traian Pop, Zebo Peng
"s" High-level architectural co-simulation using Esterel and C [p. 189]: Andre Chatelain, Yves Mathys, Giovanni Placido, Alberto La Rosa, Luciano Lavagno
"s" A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design [p. 195]: Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed A. Jerraya
"s" The TACO Protocol Processor Simulation Environment [p. 201]: Seppo Virtanen, Johan Lilius

Formal Synthesis and Code Generation of Embedded Real-Time Software [p. 208]: Pao-Ann Hsiung
Whole program compilation for embedded software: the ADSL experiment [p. 214]: Johan Cockx
Compiler-Directed Selection of Dynamic Memory Layouts [p. 219]: Mahmut Taylan Kandemir, Ismail Kadayif
"s" Logic Optimization and Code Generation for Embedded Control Applications [p. 225]: Yunjian Jiang, Robert Brayton
"s" Empirical Comparison of Software-Based Error Detection and Correction Techniques for Embedded Systems [p. 230]: R.H.L. Ong, M.J. Pont

Dynamic I/O Power Management for Hard Real-time Systems [p. 237]: Vishnu Swaminathan, Krishnendu Chakrabarty, S. S. Iyengar
"s" Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors [p. 243]: Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
"s" Processor Frequency Setting for Energy Minimization of Streaming Multimedia Applications [p. 249]: Andrea Acquaviva, Luca Benini, Bruno Ricco
"s" Retargetable Compilation for Low Power [p. 254]: Wen-Tsong Shiue
"s" A Design Framework to Efficiently Explore Energy-Delay Tradeoffs [p. 260]: William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria