This paper identifies three major issues facing worst-case execution time (WCET) reduction algorithms on adaptable architectures based on research carried out for the MCGREP-2 CPU project. The issues are exposing more instruction level parallelism (ILP) in code, reducing loading costs for the memory and processing elements used to reduce WCET, and making use of application-specific hardware. Potential difficulties in each of these areas are identified and possible solutions are proposed.
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BibTex Entry

@inproceedings{Whitham2008a,
 author = {Jack Whitham and Neil Audsley},
 booktitle = {Proc. APRES},
 pages = {8--11},
 title = {Limitations of Adaptable System Architectures for WCET Reduction},
 year = {2008}
}