Hardware Compilation of Sequential Ada
M. Ward and N. C. Audsley
Normal implementations of real-time systems on conventional processors are becoming much more difficult to prove correct to their timing specification. This is due to the complexity of modern processors (e.g. the worst case execution time of a program becomes hard to calculate in the presence of CPU speed up features such as caches and pipelines). Field Programmable Gate Arrays (FPGAs) provide a way to ease this problem by providing an implementation medium that has a simple timing model. However there is no support for real-time languages on FPGAs. This paper describes a compiler for a sequential subset of Ada95, concentrating upon compilation of subprograms and statements. It is shown how the resulting circuits give simple timing analysis. Extensions to the current compiler are explored to give support for a larger range of types and a predictable subset of the Ada95 concurrency model.
BibTex Entry
@inproceedings{Ward2001,
author = {M. Ward and N. C. Audsley},
booktitle = {Proceedings of CASES 2001},
category = {noveltechnology, languages},
pages = {99-107},
title = {Hardware Compilation of Sequential Ada},
year = {2001}
}