Exploring NoC-Based MPSoC Design Space with Power Estimation Models
L. Ost, G. M. Guindani, F. G. Moraes, L. S. Indrusiak and S. Maatta
This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.
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BibTex Entry
@article{Ost2011,
author = {L. Ost and G. M. Guindani and F. G. Moraes and L. S. Indrusiak and S. Maatta},
journal = {IEEE Design & Test of Computers},
month = {March},
number = {2},
pages = {16--29},
title = {Exploring NoC-Based MPSoC Design Space with Power Estimation Models},
volume = {28},
year = {2011}
}