Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.