MCC: Mixed Criticality Embedded Systems on Many-Core Platforms (EPSRC)

An increasingly important trend in the design of real-time and embedded systems is the integration of applications with different levels of criticality onto a common hardware platform. At the same time, these platforms are migrating from single cores to multi-cores and, in the future, many-core architectures. Criticality is a designation of the level of assurance against failure needed for a system component. A mixed criticality system (MCS) is one that has two or more distinct levels. A number of application domains, such as automotive and avionics, and EU initiatives (for example Horizon2020) have identified Mixed Criticality as a key issue in future systems.

The fundamental research question underlying these initiatives is: how, in a disciplined way, to reconcile the conflicting requirements of 'partitioning' for (safety) assurance and 'sharing' for efficient resource usage. This question gives rise to theoretical problems in modelling and verification, and systems problems relating to the design and implementation of the necessary hardware and software run-time controls. This project addresses both the theoretical and related systems questions.


Status Finished
UoY Lead Alan Burns
UoY People on Project Rob Davis, Leandro Soares Indrusiak, Iain Bate, James Harbin, Tom Fleming
Funded By EPSRC
Start Date 01-04-2013
End Date 30-10-2016
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