PhD current working title of project: Improving packet predictability of scalable network-on-chip designs without priority pre-emptive arbitration.
Research interests: With many-core processors of the future having hundreds or thousands of cores, communication is forecasted to be the major performance and power bottleneck. In such systems, Network-on-chip designs are supposed to act as the dedicated communication infrastructure for the cores thereby making them a plausible reality. I work with Network-on-Chip designs in a very low hardware level on innovations that would make data transmission through Network-on-Chip more time predictable.
Country of origin: India
Institution/country where you studied your undergraduate/masters degree(s): MSc Digital Systems Engineering, University of York; BE Electronics and Communication Engineering, Anna University Chennai.
Received the best paper award at the 9th International Symposium on Reconfigurable Communication-centre Systems-on-Chip (ReCoSoC), Montpellier, France, May 2014.
Received the best presentation award at the 7th York Doctoral Symposium on Computer Science and Electronics (YDS), York, UK, October 2014.