The ReduceronMatthew Naylor, Colin Runciman and Jason Reich
FPGA kit provided by
From October 2008 to March 2010, we worked on the EPSRC-funded project The Reduceron: High-Level Symbolic Computing on FPGA. This web-page makes available the results of the project.
The design, implementation, and evaluation of the Reduceron are described in detail in our paper
(to appear in the Journal of Functional Programming)
This is an extended version of a paper accepted to ICFP'10. Other relevent published material includes our paper Supercompilation and the Reduceron (accepted to META'10) and, from the beginning of the project, our talk proposal (accepted to HFL'09).
The benchmark programs used in our experiments are available here.
ImplementationThe implementation of the Reduceron comprises three pieces.
The following memos record our work-in-progress thoughts and ideas. In general, they are drafty in nature: some are sketchy, some are incomplete, and some are subsumed by later memos and published papers.
The Reduceron was first developed as part of Matthew's thesis, circa 2007. Here are some of the materials that arose from the thesis work.