AURA II

GRANT NUMBER: GR/L74651 START DATE: 1/8/97

DURATION: 36 months AMOUNT: £346,753

PROJECT OBJECTIVES

1. To investigate methods for scaling-up hardware implementations of neural network-based advanced associative memory developed in the original AURA project;
2. To explore the problems involved in distributing AURA tasks over a number of CMM processors;
3. To explore the problems of implementing high-speed communications within a multiprocessor environment;
4. To demonstrate the useful application of AURA in commercial/industrial pattern matching problems;
5. To demonstrate the application of the results in mission systems.

PROGRESS/DELIVERABLES:

Status at: 31/4/01.

• Phase 1
• 1.1 Design of SAT improvements. (1st milestone. Completed 1/11/97).
• 1.2 Construction of main CMM match engine card. (2nd milestone. Completed ).
• 1.3 Software architecture. (3rd milestone. Completed. New software architecture embodied in software library API specification).
• 1.4 Develop initial demonstrator. (Address Matcher demonstrator completed and fully operational).
• 1.5 PC card design and build (EO). (4th milestone. Prototype built and tested. Batch of 28 cards now built, tested and installed in Cortex-1 system).

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  Phase 2
• 2.1 VLSI  implementation. (VLSI route not cost-effective at this stage of design so enhanced FPGA design implemented.)
• 2.2 Hardware implementation of MBI. (H/w implementation of MBI not cost-effective. Improved algorithms and library routines produced).
• 2.3 Hardware implementation of pre-processing functions. (6th milestone. Implemented as improved and extended library routines).
• 2.4 Address validation demonstrator. (Completed. Several versions now implemented.)
• 2.5 BAe application demonstrator. (Alternative demonstrator implemented to show scalability:  high-performance document retrieval).
• 2.6 Documentation of the system hardware and software. (Documentation of h/w and s/w produced. Further documentation in preparatio