HIPIC

Stack machines operate upon an implicit operand stack, rather than an explicitly addressed register file. Consequently they offer some advantages in terms of code compactness, cache code-density, and simplicity of hardware. However, the concept of instruction level parallelism (ILP) has yet to be fully explored.

HIPIC, supported in part by Infineon UK Ltd, seeks to explore these issues through several avenues of research:-

    Code Analysis and Optimisation
    Development of ILP capable Stack Architectures
    Dynamic Simulation of ILP Stack machines
    Hardware Modelling

Several researchers have worked on this project to date, Huibin Shi explored code analysis and optimisation for stack ILP paradigms, assisted by Soyeb Alli.  My own research efforts are directed toward development of new machine architectures, and simulation tools to establish performance benchmarks Dr Shi has now taken a position at the Nanjing Aeronautical and Astronautical University of Nanjing, P.R. China (NAAU).