[Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'logic.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'ctl_in_3_A' based upon the LOC constraint 'P43'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. |
[Warning]:Cpld:1239 - The global clock designation (BUFG) on signal 'ctl_out_3_A_OBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. |