Design Name | logic |
Device, Speed (SpeedFile Version) | XC9572XL, -5 (3.0) |
Date Created | Wed Dec 14 09:00:25 2016 |
Created By | Timing Report Generator: version P.20131013 |
Copyright | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Pad to Pad Delay (tPD) | 5.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 5.0 | 13 | 13 |
AUTO_TS_P2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2P | 0.0 | 0.0 | 0 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
ctl_in_1_A to ctl_out_1_A | 0.000 | 5.000 | -5.000 |
ctl_in_1_A to ctl_out_1_B | 0.000 | 5.000 | -5.000 |
ctl_in_1_B to ctl_out_1_A | 0.000 | 5.000 | -5.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Source Pad | Destination Pad | Delay |
---|---|---|
ctl_in_1_A | ctl_out_1_A | 5.000 |
ctl_in_1_A | ctl_out_1_B | 5.000 |
ctl_in_1_B | ctl_out_1_A | 5.000 |
ctl_in_1_B | ctl_out_1_B | 5.000 |
ctl_in_2_A | ctl_out_2_A | 5.000 |
ctl_in_2_A | ctl_out_2_B | 5.000 |
ctl_in_2_B | ctl_out_2_A | 5.000 |
ctl_in_2_B | ctl_out_2_B | 5.000 |
ctl_in_3_A | ctl_out_3_A | 5.000 |
sw_1_A | ctl_out_1_A | 5.000 |
sw_1_B | ctl_out_1_B | 5.000 |
sw_2_A | ctl_out_2_B | 5.000 |
sw_2_B | ctl_out_2_A | 5.000 |