********** Mapped Logic ********** |
ctl_out_1_A <= (ctl_in_1_A AND NOT sw_1_A AND NOT ctl_in_1_B); |
ctl_out_1_B <= (NOT ctl_in_1_A AND ctl_in_1_B AND NOT sw_1_B); |
ctl_out_2_A <= (ctl_in_2_A AND NOT sw_2_B AND NOT ctl_in_2_B); |
ctl_out_2_B <= (NOT ctl_in_2_A AND ctl_in_2_B AND NOT sw_2_A); |
ctl_out_3_A <= ctl_in_3_A; |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |