Re: Safety of ASICs



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Neil Audsley (Neil.Audsley(at)cs.york.ac.uk)
Thu, 23 Dec 1999 22:11:02 +0000


Interesting debate .. John McDermid wrote: > > > > Rod Muttram at a railway seminar last year was pushing the concept that it > > wasn't the hardware that was important but that in the life of the > > signalling system (approximately 25-30 years) the hardware will become > > obsolete and the software will need "porting" elsewhere. > > This is part of the logic behind the ASIC design. By having a processor > core in VHDL, you can port to a new fab. technology, get a faster CPU ... > without redesign. That's one of the many factors. Hold on - this is exactly the object code verification problem again, only at a lower level -> VHDL has to be translated to gate layout for fabrication. You may get away with _some_ redesign, but you will still need to show some properties of the fabricated device. > > Is effort therefore better directed at looking for a software platform > that > > is independent of the hardware, rather than adapting current hardware? I certainly agree with Peter's point here. Processor failures are not particularly significant compared to other failures (sensors, software etc). -- ========================================================================= Dr. Neil C. Audsley Email: neil(at)cs.york.ac.uk Senior Research Fellow Phone: +44-1904-432787 Department of Computer Science, Fax: +44-1904-432708 University of York, York. Y01 5DD, UK


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