The Reduceron
Matthew Naylor and
Colin Runciman
Between October 2008 and December 2009, we are working on the
EPSRC-funded project
The Reduceron: High-Level Symbolic
Computing on FPGA,
continuing work that began in Matthew's thesis. This web-page makes
available the work-in-progress results of the project.
Technical report
Coming soon...
Implementation
The implementation of the Reduceron comprises three pieces.
| York Lava |
The Haskell library used to describe the Reduceron |
| F-lite |
A compiler for the language that runs on the Reduceron |
| Reduceron |
The reduction machine itself |
F-lite and York Lava are discussed in memos
9 and
23 respectively.
Memos
The following series of memos are just notes, mainly for our own
benifit.
Previous work
The Reduceron was first developed as part of Matthew's thesis,
circa 2007. Here are some of the materials that arose from the thesis
work.
|